As electronic structures become smaller, it appears that the challenges become larger. (Remember the predictions that optical lithography was obsolescent? We have heard this for some 30 years or so.) Our attention usually focuses on transistor gate lengths, oxide thicknesses, etc. The cases of nano-dot junctions and nano-wires may be rather different.
Firstly, it is hard to know what it is we make, when we create a particle that is only a few atoms wide. As this reference explains [1], standard methods like X-ray or neutron scattering work well for bulk, crystalline materials but not for clusters or for amorphous solids. However, by introducing plausible constraints and by utilizing multiple sources of experimental and theoretical information, one may obtain an average or representative structure. But doing so is by no means a trivial undertaking. I think that similar results obtain for the case of nano-wires as well.
Secondly, our understanding of devices must evolve at the nano-scale. The instantaneous electron temperature of a nano-device plays a huge role in the device noise. However, the electron temperature in a nano-device often differs greatly from the lattice temperature. The paper here [2] argues that at the transition between single-electron conduction and mixed single- and multiple-electron conduction, the signal/noise ratio becomes exceptionally small, far more so than one would expect by considering the lattice temperature alone.
In conventional devices, we tend to see digital transistors switched as rapidly as possible in order to maximize speed and to avoid the “unknown” state. But in a nano-scale device, this is exactly the wrong thing to do! This paper [3] shows that nano-transistors must be switched adiabatically in order to avoid driving the device into high-frequency oscillation. We have yet to learn how slowly the switching must be in order to be considered adiabatic.
Circuit designers and manufacturers have worked around electromigration failure, largely by controlling uniformity, roughness, and material composition, and by giving every conductor some extra size margin. If we think of scaling our wires down to a few nanometers, other challenges arise.
When the radius of a silicon nano-wire is somewhere around 10nm or smaller, we expect significant divergences from bulk electronic behavior, according to this review [4]. For example, the scattering radius of an impurity (be it defect or dopant) may be as large as the radius of the nano-wire. This results in very low longitudinal conductivity, since electrons completely backscatter from the impurity.
Toshiba seems to have made a significant advance by creating a nano-wire transistor channel with dimensions around 14nm X 20nm [5]. This is a bit larger than our discussion above, but not much. Review [4] also contains a discussion of why particular crystal orientations within the nano-wire are much preferred over other orientations. Toshiba apparently chose to run their channel along the <100> direction.
We should also expect, as a result of the high surface to volume ratio of a nano-wire, that the mechanical properties also differ from those of the corresponding bulk materials. This experimental study of gold wires [6] warns us of the difficulties that lie ahead for semiconductor devices design and manufacturing.
[1] http://arxiv.org/abs/0912.1971
(Synopsis) http://physics.aps.org/articles/v3/25
[2] http://arxiv.org/abs/0912.2832
(Synopsis) http://physics.aps.org/synopsis-for/10.1103/PhysRevLett.104.196805
[3] http://arxiv.org/abs/0911.3870
(Synopsis) http://physics.aps.org/articles/v3/47
[4] http://arxiv.org/abs/0910.2553
[5] http://www.toshiba.co.jp/about/press/2010_06/pr1501.htm
[6] http://arxiv.org/abs/0910.4139
