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The SPIE Advanced Lithography Conference was dominated this year by incremental progress. I paid most attention to the e-beam patterning sessions, running off for a few other interesting papers.

Possibly the most exciting development was Paper 7970-14, “Self-assembly patterning for sub-15 nm half-pitch”, reporting joint work from Applied Materials and IBM Almaden. Chris Bencher showed a directed self-assembly process which resulted in etched patterning on silicon wafers. Using polystyrene-block-polymethylmethacrylate pinned by patterned BARC, Mr Bencher showed chip-area, periodic patterns at very high resolution. Defectivity is acceptable for this point in the R&D effort, comparable to the early days of 193i R&D. Interestingly, the defects are mostly particles, not self-assembly errors (except adjoining the streets).

In e-beam, the REBL project appeared much more convincing this time around. [Paper 7970-43, "New advances with REBL for maskless, high-throughput EBDW lithography"] Paul Petric (KLA-Tencor) reported that beam down on column design #2 was due during the week of the conference. He reported some difficulties with getting a functional modulator assembly, but sounded optimistic that the difficulties would be resolved shortly. An architectural overview may be found in [J. Vac. Sci. Technol. B 28, C6C6 (2010); doi:10.1116/1.3511436].

To my friends and colleagues in Japan, I extend my deep sympathy to all those who suffer in the aftermath of this great earthquake.

- Richard L Lozes

Reading this article in the LA Times today, I could not help but think of all the hollowed out semiconductor equipment companies in Silicon Valley. The SEMI heavyweights  have been outsourcing for years, shedding ever more employees and expertise. Is it any wonder that there are no leading-edge vendors of lithography equipment in the U.S. anymore?

In a related vein, Gio Wiederhold (Stanford Univ.) details the process by which U.S. companies set up foreign subsidiaries strictly for the purpose of holding the company I.P. (patents, for example). Why? Simply to fluff up the finances and avoid U.S. taxes. (The paper is also available from Prof. Wiederhold’s home page.)

We can rest assured that all the hot air about job creation will come to naught until the rules of the game change.

Serendipitous update: See the just published article by Dominic Barton in Harvard Business Review on “Capitalism for the Long Term”.

BACUS, officially known as the SPIE/BACUS Photomask Symposium, held an all-day session on electron beam direct write.

My overall impression of this special session was that there has been excellent progress on direct write (or “maskless”) pattern generation. However, it is clear that there remain important unresolved issues.

Sematech’s position (Stefan Wurm) is that there is no supporting infrastructure, in particular there is no clear solution for pattern inspection. We are accustomed to inspecting every feature on masks. But the mask is replicated many times without inspecting every feature on the wafers. In the case of direct write, must we inspect every feature on every wafer? This is clearly impossible. Thus Sematech now pursues multi-beam mask write in support of EUV.

As if in answer, Wolfgang Staud (Applied Materials) reported on the multi-column inspection tool being built in Germany. The current challenges include data transfer and data compaction.

Data handling was also addressed by Tor-Björn Sandström (Micronic), albeit for patterning rather than inspection. He reported that Micronic and ASML decided not to proceed with a 65 nm direct write laser PG because of data handling issues. He extrapolates to the 16 nm node, and claims that in order to displace EUV, one needs to transfer 160 Tpixel / second (160 * 10^12) in gray scale. Already at the 65 nm node, Micronic could not transfer data fast enough to compete with optical scanners.

At the same time, Berglund (consultant), Aki Fujimura (D2S), and Akio Yamada (Advantest) all argued that for small wafer volumes, direct write will be economical and will continue to be used. None of these talks addressed the issue of pattern inspection. Indeed, does e-Shuttle perform full pattern inspection on wafer production now? Did previous ASIC and custom direct write fabs perform full pattern inspection?

Perhaps these issues of data handling and pattern inspection are over-estimated now.