Accustomed to the semiconductor world, I was intrigued to find a preprint touting 72,800 superconducting devices on a single chip. It turns out that superconducting technology, although capable of extremely fast switching, has been plagued by a number of obstacles, such as large current draw due to bias resistors, non-planarized manufacturing processes, and trapped flux. Stochastic flux trapping during cool-down leaves the devices in unequal states to begin with, rendering a circuit possibly inoperable, even if perfectly manufactured.
MIT Lincoln Labs has largely overcome the first two problems with their recently announced process, while Northrup Grumman has demonstrated a chip holding a pair of long shift registers with the desired low-to-zero flux trapping. Poking around the literature, I find that a group of Japanese universities in conjunction with AIST demonstrated similar processing and device count a year ago. There is a corresponding effort in Europe.
There is a informative, summary outlook available from NSA.
By the way, these devices all look to be fabricated “upside down”: whereas semiconductor devices put the active gates at the bottom and build wiring on top, superconducting devices put the wiring below and the active junctions on top.
 Q Herr, et al., “Reproducible Operating Margins on a 72,800-Device Digital Superconducting Chip”, arXiv:1510.01220
 S Tolpygo, et al., “Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits”, 12th European Conference on Applied Superconductivity EUCAS 2015, arXiv:1509.05081
 S Nagasawa, et al., “Nb 9-layer fabrication process for superconducting large-scale SFQ circuits and its process evaluation”, IEICE Trans. Electron., vol. E97-C, No. 3, pp. 132-140, March 2014. PDF
 MIT Lincoln Laboratory, “Forecasting superconductive electronics technology”, The Next Wave, Vol. 20, No. 3, 2014